It is often practical to implement a high-speed analog-to-digital converter (ADC) by time interleaving multiple lower speed ADCs, called ADC slices. For example, FIG. 1 shows a high-speed ADC 100 implemented by multiple ADC slices #0 through #N-1. ADC slices #0 through #N-1 each operate at a slice sampling rate fslice, and they sample an analog input signal Ain in round robin fashion such that the aggregate of the sampling rates of the ADCs is equal to a desired higher overall sampling rate fADC. Lower rate digital outputs Douti of the ADC slices are processed by corresponding digital signal processors (DSPs) and then combined to reconstruct a desired higher rate digital output stream Dout.
Among the ADC slices, overall gain gi, overall offset oi, sampling timing instant, input sampling bandwidth, and various other transfer function related attributes may differ due to practical manufacturing tolerances, and these differences may limit the achievable performance of ADC 100. As an example, offset mismatches between ADC slices manifest as frequency domain spurs in the digital output of the interleaved ADC at multiples of the slice clock frequency independent of the applied input. Similarly gain mismatches between ADC slices causes the input signal to be modulated by different gains at each time step resulting in frequency domain spurs that look like images of the applied input signal.
Various researchers have studied the effect of these and other interleaving errors and have developed methods to address them. Many of these methods rely on assumptions about the characteristics or statistical properties of the input that may be specific to the overall system in which these ADCs are designed to operate. These assumptions, however, do not necessarily hold true in instrumentation applications where it is not possible for an instrument designer to impose such restrictions on the user. Moreover, calibration techniques used for ADCs targeted to be used in measuring instruments should be robust and cannot rely on the externally applied input signal. As an example, some inter-slice offset calibration algorithms converge incorrectly when the intentional input signal contains a time invariant component like a signal at 0 Hz or a signal that looks like a time invariant input to an ADC slice like a sinusoid at the slice clock rate or at multiples of the slice clock rate. In other words, sub-harmonics of the overall sampling rate alias to a signal at 0 Hz at the input to the ADC slice. Similarly, some inter-slice gain calibration algorithms converge incorrectly when there is no applied signal i.e. the ADC has an idle input.
An alternative calibration approach inserts a pseudo-random dither sequence D and performs a pseudo-random chopping operation in a signal path common to all ADC slices. The inserted dither is used to estimate and correct inter-slice gain errors, and the pseudo-random chopping operation is used to estimate and correct inter-slice offset errors. The estimation and correction is performed continuously, while the desired input samples are converted by the interleaved ADC, and is termed background calibration. The dither insertion and signal-path chopping operations allow the inter-slice gain and inter-slice offset calibrations to operate in a manner independent of the characteristics of the input signal.
In the above approach, semiconductor devices in the signal path heat in a manner that depends upon the signal through these devices. In circuits prior to the chopping operation, this phenomenon results in an error termed as a thermal tail and can be observed as a slow settling behavior in time-domain step response or a filtering effect at low frequencies, because the thermal time constants are much slower than electrical time constants. The thermal tail is a linear effect and can be appropriately characterized and specified. However for circuits after the chopping operation, this slow/low frequency tail gets modulated by the pseudo-random broadband chopping signal and results in a pseudo-randomly modulated thermal tail that spreads throughout the conversion bandwidth. This resembles a broadband noise and severely degrades the signal-to-noise ratio (SNR) of the overall ADC.
In view of at least the above shortcomings of conventional approaches, there is a general need for new approaches for calibrating gain and voltage offsets in interleaved ADCs.